Title :
Design and optimization of 0.25μm technology low-voltage low-power CMOS APS with device scaling considerations
Abstract :
The device scaling makes the power supply voltage reduced to obtain low power dissipation. But the low power supply voltage reduces the pixel readout signal voltage swing and has an immense impact on the signal-to-noise ratio, the readout speed and the dynamic range of CMOS APS. In this paper we presented a complete analysis and optimization of wide-output-swing high-readout-speed CMOS APS. Using a PMOSFET to substitute the NMOSFET reset transistor, a threshold voltage (Vt) loss is saved. By analyzing and optimizing the pixel circuit, the optimization transistor size has been obtained. Based on the 0.25 μm 2P3M CMOS image sensor technology of the Dongbu foundry and the HSPICE simulator in Synopsys software, the results show that the output swing is improved about 0.65185V and the settling time is saved about 28.91 ns. It means to enlarge the dynamic range and to increase the readout speed.
Keywords :
CMOS image sensors; MOSFET; circuit optimisation; integrated circuit design; low-power electronics; network analysis; readout electronics; 0.25 micron; 2P3M CMOS image sensor technology; CMOS active pixel sensor; Dongbu foundry; HSPICE simulator; NMOSFET reset transistor; PMOSFET reset transistor; Synopsys software; complementary metal oxide semiconductor; device scaling; field effect transistor; high readout speed CMOS APS; low power dissipation; low voltage low power CMOS APS; metal oxide semiconductor FET; pixel circuit analysis; pixel circuit optimization; pixel readout signal voltage; power supply voltage; settling time; signal-to-noise ratio; threshold voltage loss; transistor size;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277620
