Title :
An effective bus-based arbiter for processors communication
Author :
Tu, Jih-Fu ; Chen, Chih-Yung
Author_Institution :
Dept. of Electron. Eng., St. John´´s & St. Mary´´s Inst. of Technol., Taiwan
Abstract :
Multiprocessor system is made up of two or more main processing elements with similar capabilities running under a single operation system, and the processing elements communicate and cooperate with each other when data or control dependency. We discuss how to implement an affective multiple buses arbiter for the multiprocessor system. The arbitration of bus is based on two-stage arbitration logic control in interprocessor communication network. For the performance comparison, we analyze the message-transmission rate among processors for the proposed arbiter and the crossbar-based ones.
Keywords :
multistage interconnection networks; shared memory systems; system buses; bus-based arbiter; interprocessor communication network; message-transmission rate; multiple buses arbiter; multiprocessor system; processing element; processors communication; two-stage arbitration logic control; Communication networks; Communication system control; Control systems; Logic; Multiprocessing systems; Performance analysis;
Conference_Titel :
Advanced Information Networking and Applications, 2004. AINA 2004. 18th International Conference on
Print_ISBN :
0-7695-2051-0
DOI :
10.1109/AINA.2004.1283794
