DocumentCode
408417
Title
Low-power CMOS circuits for analog VLSI programmable neural networks
Author
El-soud, Mohy A. ; AbdelRassoul, Roshdy A. ; Soliman, Hassan H. ; El-ghanam, Laila M.
Author_Institution
Dept. of Electron. & Commun. Eng., Mansoura Univ., Egypt
fYear
2003
fDate
9-11 Dec. 2003
Firstpage
14
Lastpage
17
Abstract
This paper presents an analog VLSI neural network for designing a programmable neural system. Synaptic weights are designed in the triode region using four-MOS transistors. Moreover, the summing element (SE) and the activation function are designed in subthreshold region. This system is realized in a standard 0.8 μm CMOS technology and operated with a ±1V power supply.
Keywords
CMOS integrated circuits; MOSFET; VLSI; neural nets; semiconductor device models; summing circuits; 0.8 micron; CMOS technology; MOS transistors; analog VLSI programmable neural networks; low-power CMOS circuits; subthreshold region; summing element; Artificial neural networks; CMOS analog integrated circuits; CMOS technology; Handwriting recognition; MOSFETs; Neural networks; Neurons; Strontium; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on
Print_ISBN
977-05-2010-1
Type
conf
DOI
10.1109/ICM.2003.1287711
Filename
1287711
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