An RTL Verilog processor

Author

Jamal, Habibullah ; Khan, Shoab ; Hameed, Fahed ; Saeed, Sharjeel ; Pasha, Moazzam

Author_Institution

Center for ASIC Design & Digital Signal Process., Univ. of Eng. & Technol., Taxila, Pakistan

fYear

2003

fDate

9-11 Dec. 2003

Firstpage

23

Lastpage

26

Abstract

This paper presents a processor that efficiently executes Verilog code written at Register Transfer Level (RTL). It is a RISC type processor that performs the parallel execution of multiple procedural blocks of Verilog HDL. This results in a very significant saving of simulation time. The simulation time taken by the software based simulation in terms of clock cycles on a normal Pentium Processor is Million times more than taken by this processor built on an FPGA.

Keywords

digital simulation; field programmable gate arrays; hardware description languages; parallel processing; reduced instruction set computing; FPGA; HDL; Pentium Processor; RISC type processor; RTL Verilog processor; field programmable gate arrays; hardware description languages; reduced instruction set computing; register transfer level; software based simulation; Acceleration; Application specific integrated circuits; Circuit simulation; Counting circuits; Hardware design languages; Process design; Processor scheduling; Registers; Switches; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on

Print_ISBN

977-05-2010-1

Type

conf

DOI

10.1109/ICM.2003.1287713

Filename

1287713