ARM/THUMB code compression for embedded systems

Author

Xu, X.H. ; Jones, S.R. ; Clarke, C.T.

Author_Institution

Fac. of Eng. & Design, Univ. of Bath, UK

fYear

2003

fDate

9-11 Dec. 2003

Firstpage

32

Lastpage

35

Abstract

The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.

Keywords

data compression; embedded systems; memory architecture; reduced instruction set computing; RISC; data compression algorithm; embedded systems; memory compression architecture; reduced instruction set computing; size reduction; Application software; Code standards; Computer architecture; Costs; Data compression; Embedded system; Instruction sets; Memory architecture; Reduced instruction set computing; Thumb;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on

Print_ISBN

977-05-2010-1

Type

conf

DOI

10.1109/ICM.2003.1287715

Filename

1287715