Title :
Multilevel logic multiplier using VLSI neural network
Author :
Pan, Huadian ; Manic, Milos ; Xiangli Li ; Wilamowski, Bogdan
Author_Institution :
Graduate Center at Boise, Idaho Univ., Boise, ID, USA
Abstract :
This paper presents a solution for digital multiplier implemented with cascade connected neural network architecture. Proposed solution uses multilevel logic where information is compressed. To facilitate VLSI implementation, low voltage current mode operation is being used in this paper. Multiplier design is presented as a summator where the result is provided in one clock cycle. The system is fully simulated with SPICE and the chip is fabricated in the AMI 1.5 μm MOSIS process.
Keywords :
SPICE; VLSI; digital arithmetic; multivalued logic; neural net architecture; VLSI neural network; cascade connected neural network architecture; digital multiplier; low voltage current mode operation; multilevel logic; multilevel logic multiplier; Analog-digital conversion; Clocks; Computational modeling; Computer architecture; Hardware; Logic; Low voltage; Neural networks; Neurons; Very large scale integration;
Conference_Titel :
Industrial Technology, 2003 IEEE International Conference on
Print_ISBN :
0-7803-7852-0
DOI :
10.1109/ICIT.2003.1290318
