A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability in static random access memory (SRAM) cells. This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages V_DD. The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work.