A prototype architecture for the accurate modeling of Rayleigh fading waveforms

Architecture and circuit design techniques for VLSI implementation of a single-chip wide-band Rayleigh fading emulator with improved statistics along with a variable fade rate and high bit rates are presented. The circuit is realized using efficient algorithms with suitable modifications for algorithm-to-architecture mapping. The design uses parallel architecture and ROM compression techniques for the generation of conditionally random Doppler frequencies. This design has been found suitable for FPGA implementation and explores the possibility of improving the accuracy of available DSP based emulators. The chip implementation for the emulator will support bit rates of 5 Mbps, fade rates of 5 kHz and up to a delay of six taps. The use of a sigma-delta converter to increase the dynamic range and the overall SNR performance of the emulator is also investigated.