Title :
Scaling trends in DRAM technology
Author_Institution :
IBM Microelectron., Hopewell Junction, NY, USA
Abstract :
Summary form only given. Trends in scaling DRAM to 0.11 μm and below are reviewed. Scaling techniques used in earlier generations for the array access transistor and the storage capacitor are running into limitations, necessitating changes in electrical operating mode, cell structure, and processing innovations. Although a variety of options exist for advancing the technology, including low-voltage operation, non-planar array transistor MOSFETs, and novel capacitor structures and materials, uncertainties exist over the which of these will prove workable in manufacturing. This paper discusses the interrelationships among the DRAM scaling requirements and solutions.
Keywords :
DRAM chips; MOS memory circuits; low-power electronics; 0.11 micron; DRAM technology scaling trends; array access transistor; low-voltage operation; nonplanar array transistor MOSFET; storage capacitor structure; Capacitors; MOSFETs; Manufacturing; Microelectronics; Random access memory; Technological innovation; Transistors; Uncertainty;
Conference_Titel :
Microelectronics and Electron Devices, 2004 IEEE Workshop on
Print_ISBN :
0-7803-8369-9
DOI :
10.1109/WMED.2004.1297339
