A 3–25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA

Author

Yu-Hsun Chien ; Kuan-Lin Fu ; Shen-Iuan Liu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

61

Issue

11

fYear

2014

fDate

Nov. 2014

Firstpage

845

Lastpage

849

Abstract

A 3-25 Gb/s four-channel receiver with noise-canceling transimpedance amplifiers and power-scalable limiting amplifiers is presented. It is fabricated in a 40-nm CMOS process. Each channel provides an overall gain of 64 dB · Ω. The measured input integrated noise is 2.7 μA_rms, and the measured bit error rate is <; 10^-12 for a 25-Gb/s pseudorandom bit sequence of 2⁷-1. The power consumption is 103 mW per channel from a 1.3-V supply. The total area is 1.16 mm².

Keywords

CMOS integrated circuits; error statistics; low-power electronics; operational amplifiers; random sequences; CMOS process; bit error rate; bit rate 3 Gbit/s to 25 Gbit/s; four-channel receiver; limiting amplifiers; noise canceling TIA; power 103 mW; power scalable LA; pseudorandom bit sequence; size 40 nm; transimpedance amplifiers; voltage 1.3 V; Bandwidth; Bit rate; CMOS integrated circuits; CMOS technology; Noise cancellation; Receivers; Limiting amplifier (LA); noise canceling; power scalable; transimpedance amplifier (TIA);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2014.2350372

Filename

6882147