DocumentCode :
41286
Title :
A 0.5-V, 1.47- 
40-kS/s 13-bit SAR ADC With Capacitor Error Compensation
Author :
Hyunsoo Ha ; Seon-Kyoo Lee ; Byungsub Kim ; Hong-June Park ; Jae-Yoon Sim
Author_Institution :
Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol. (POSTECH), Pohang, South Korea
Volume :
61
Issue :
11
fYear :
2014
fDate :
Nov. 2014
Firstpage :
840
Lastpage :
844
Abstract :
A 13-bit successive approximation analog-to-digital converter (ADC) is presented for an ultralow-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in a digital-to-analog converter. The ADC is implemented in a standard 0.13-μm CMOS. With a single supply voltage of 0.5 V and a rail-to-rail conversion range, the ADC dissipates 1.47 μW at a sampling rate of 40 kS/s. It shows a figure of merit of 17.9 fJ/conversion-step with an effective number of 11.0 bits.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; SAR ADC; capacitor banks; capacitor error compensation; digital-to-analog converter; power 1.47 muW; rail-to-rail conversion range; size 0.13 mum; standard CMOS; successive approximation analog-to-digital converter; ultra low-power sensor interface; voltage 0.5 V; word length 13 bit; CMOS integrated circuits; Calibration; Capacitors; Error compensation; Measurement uncertainty; Noise; Thermal noise; Capacitor mismatch compensation; high resolution; sensor interface; successive approximation register (SAR), analog-to-digital converter (ADC); ultralow power;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2014.2350378
Filename :
6882154
Link To Document :
