Performance of 155Mbps clock/data recovery circuits on heavy loaded PLDs

Author

Figueiredo, Monica ; Aguiar, Rui L.

Volume

2

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

511

Abstract

This paper discusses the performance of internal clock and data recovery mechanisms integrated in low-cost FPGA environments. Two designs are used for this analysis, using a data sampling system with phase detection and decision logic to select the most appropriate sample either as the recovered data or as the most appropriate phase for the recovered clock. These mechanisms have been implemented in low cost PLDs from major manufactures. These PLDs have been heavily loaded with typical communications circuit functions, and the performance of the clock/data recovery circuits has been analyzed. The results show that different architectures behave differently, but internal noise can significantly impair the performance of the circuit. This poses large difficulties to the re-usage of these blocks as virtual components.

Keywords

clocks; field programmable gate arrays; integrated circuit noise; jitter; phase detectors; synchronisation; 155 Mbit/s; Xilinx Virtex-E device; bit error rate; clock recovery mechanisms; data recovery mechanisms; data sampling system; decision logic; heavy loaded PLD; internal noise; internal recovery mechanisms; low cost programmable logic devices; low-cost FPGA; phase detection; phase picking; quantization jitter; sampling clock; virtual components; Circuit analysis; Clocks; Costs; Data analysis; Field programmable gate arrays; Logic design; Manufacturing; Performance analysis; Phase detection; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301834

Filename

1301834