A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data recovery circuit

A 4Gb/s power and area efficient clock/data recovery (CDR) circuit is proposed. Fully-differential design is employed to reject any common mode noises and to significantly reduce power/ground bounce. An analog dual delay-locked loop (DLL) architecture continuously aligns the clock sampling edge to the center of incoming data eye-opening. A self-correcting function prevents the phase capture range limitation of traditional DLLs. The prototype circuit is implemented in 0.18um CMOS technology. Using 0.18μm CMOS technology, the CDR occupies a small area of 200 × 320um² and dissipates low power of 27mW from 2V power supply.