Title :
Building blocks for a 100 MS/s, 10-b, 1.8 V CMOS cascaded folding & interpolating A/D converter
Author :
Kokozidis, Ch ; Bouras, S. ; Arapoyanni, A.
Author_Institution :
Dept. of Informatics & Telecommun., Univ. of Athens, Ilisia, Greece
Abstract :
This paper describes building blocks of an A/D converter, based on the folding and interpolation techniques, for mobile and wireless telecommunication applications. The differential difference technique is used to double the dynamic input range and relax the circuit design for low voltage applications. The blocks are designed in a standard 1.8 V 0.18 μm CMOS technology. The maximum sampling rate of the converter is 100 MS/s and the differential input voltage range is 2 V peak-peak.
Keywords :
CMOS integrated circuits; analogue-digital conversion; cascade networks; circuit simulation; integrated circuit design; integrated circuit modelling; interpolation; low-power electronics; mobile radio; radio equipment; signal sampling; 0.18 micron; 1.8 V; 10 bit; 2 V; CMOS cascaded folding and interpolating A/D converter; building blocks; circuit design; differential difference technique; differential input voltage range; dynamic input range; low voltage applications; maximum sampling rate; mobile telecommunication applications; standard CMOS technology design; wireless telecommunication applications; CMOS digital integrated circuits; CMOS technology; Circuit synthesis; Dynamic range; Informatics; Interpolation; Low voltage; Neodymium; Sampling methods; Signal generators;
Conference_Titel :
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
Print_ISBN :
0-7803-8163-7
DOI :
10.1109/ICECS.2003.1301906
