A boosted wordline voltage generator for low-voltage memories

Author

Chua-Chin Wang ; Hsueh, Ya-Hsin ; Ting-Wan Kuo ; Hu, Ron

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

2

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

806

Abstract

A novel voltage tripler using 4 clocks with different phases is present in this work. Both the positive and negative polarities of the voltage are generated to serve as the boosted voltage and the back bias voltage. The proposed design is carried out by pass transistors and switched capacitors. The largest generated voltages which the proposed design can provide is +11.09 V and -10.62 V given VDD=3.3 V when the circuit is implemented by TSMC 0.35 μm 1P4M CMOS technology.

Keywords

CMOS integrated circuits; CMOS memory circuits; circuit simulation; clocks; integrated circuit design; integrated circuit measurement; low-power electronics; switched capacitor networks; voltage multipliers; -10.62 V; 0.35 micron; 11.09 V; 3.3 V; TSMC 1P4M CMOS technology; back bias voltage; boosted voltage; boosted wordline voltage generator; clock phases; generated voltages; low-voltage memories; negative voltage polarities; pass transistors; positive voltage polarities; switched capacitors; Boosting; CMOS technology; Capacitors; Charge pumps; Circuits; Clocks; Computer hacking; Nonvolatile memory; Random access memory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301909

Filename

1301909