Title :
Low power high speed I/O interfaces in 0.18 μm CMOS
Author :
Yan, Ying ; Szymanski, Ted H.
Author_Institution :
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
Abstract :
The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 μm CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.
Keywords :
CMOS integrated circuits; circuit simulation; high-speed integrated circuits; integrated circuit design; integrated circuit testing; low-power electronics; 0.18 micron; 1.8 V; 10 mA; 4 Gbit/s; CMOS design; CMOS low power high speed I/O interfaces; CMOS technology; Cadence Spectre post-layout simulations; data rate; differential signaling input/output interface; performance comparisons; prototype chip; signal transmission swings; signaling technologies; Bridge circuits; Circuit synthesis; Current supplies; Design optimization; Feedback control; Resistors; Switches; Switching circuits; Transmitters; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
Print_ISBN :
0-7803-8163-7
DOI :
10.1109/ICECS.2003.1301914
