A protection mechanism for intellectual property rights (IPR) in FPGA design environment

One of the major difficulties in offering new VLSI designs is protecting the designer´s intellectual property rights (IPR). It often requires limited field deployment and testing before a novel implementation may be accepted for general use. The difficulty arises in the need to deploy the design for testing while disabling the tester from deciphering the design details. A similar requirement applies when the designer is interested in limiting the number of deployments as part of a business agreement. This work leverages the similarities between the issues of IPR protection in the hardware and software arenas and presents a novel solution to protect the use of designs in the FPGA hardware environment. The mechanisms used are based on hardware-supported design encryption and secured authentication protocols.