Title :
A VLSI architecture for minimizing the transmission power in OFDM transceivers
Author :
Babionitakis, K. ; Dagres, Y. ; Nakos, K. ; Reisis, D.
Author_Institution :
Nat. & Kapodistrian Univ. of Athens, Greece
Abstract :
This paper presents a VLSI architecture for optimizing the transmission power required in turbo-Coded Orthogonal Frequency Division Multiplexing modems. The technique adapts the transmission parameters according to the Quality of Service requirements. CORDIC computations are used to improve the VSLI area. The architecture performs at wire-speed, uses minimal area and has shown the performance gain in an indoor wireless application. An implementation using Field Programmable Gated Array technology has validated the results.
Keywords :
OFDM modulation; VLSI; field programmable gate arrays; indoor radio; modems; parallel architectures; pipeline arithmetic; quality of service; telecommunication computing; transceivers; CORDIC computations; FPGA implementation; OFDM transceivers; Supervisor module; VLSI architecture; bit-error-rate; bit-pipelining; indoor wireless application; iterative bisection technique; minimal area; parallel architecture; performance gain; quality of service requirements; transmission power; turbo-coded OFDM modems; wire-speed; Bit error rate; Computer architecture; Equations; Field programmable gate arrays; Modems; OFDM; Power dissipation; Quality of service; Transceivers; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
Print_ISBN :
0-7803-8163-7
DOI :
10.1109/ICECS.2003.1302038
