Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET]

Author

Rideau, D. ; Dray, A. ; Gilibert, F. ; Agut, F. ; Giguerre, L. ; Gouget, G. ; Minondo, M. ; Juge, A.

Author_Institution

Central R&D, STMicroelectronics, Crolles, France

fYear

2004

fDate

22-25 March 2004

Firstpage

149

Lastpage

154

Abstract

We present measurements of GIDL at various temperatures and terminal biases. Besides band-to-band (BBT) tunneling leakage observed at high drain-to-gate voltage V_DG, we also observed trap-assisted-tunneling (TAT) leakage currents at lower V_DG. Based on ISE TCAD simulations of the electric field, we propose analytical models for BBT and TAT GIDL currents suitable for compact modelling.

Keywords

MOSFET; leakage currents; semiconductor device measurement; semiconductor device models; technology CAD (electronics); tunnelling; BBT; GIDL characterization; GIDL modeling; MOSFET; TAT; band-to-band tunneling leakage; compact modelling; drain-to-gate voltage; electric field TCAD simulations; gate-induced-drain-leakage; junction leakage current; low electric field GIDL; terminal bias; trap-assisted-tunneling; Current measurement; Fluid flow measurement; Leakage current; MOSFETs; Microelectronics; Research and development; Temperature dependence; Testing; Thickness measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on

Print_ISBN

0-7803-8262-5

Type

conf

DOI

10.1109/ICMTS.2004.1309469

Filename

1309469