Design and implementation of the POWER5™ microprocessor

POWER5^TM is the next generation of IBM´s POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBM´s 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5´s dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised ∼20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chip´s frequency, area, power, and thermal targets.