Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation

Author

Takayanagi, Toshinari ; Shin, Jinuk Luke ; Su, Jeffrey ; Leon, Ana Sonia

Author_Institution

Sun Microsystems, Inc., Sunnyvale, CA, USA

fYear

2004

fDate

2004

Firstpage

147

Lastpage

150

Abstract

A processor core, originally designed in a 0.5μm Al process, is redesigned for a 0.13μm Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.

Keywords

CMOS digital integrated circuits; integrated circuit design; leakage currents; microprocessor chips; multi-threading; 64 bit; CMOS process; UltraSPARC microprocessor; compute-dense server; coupling noise; deep-submicron design challenges; dual-core microprocessor implementation; integrated L2 cache; intra die process variation; leakage; memory controller; multi-thread processor; negative bias temperature instability; performance to power ratio; processor core porting; symmetric multiprocessor bus; Computer applications; Computer networks; Coupling circuits; Microprocessors; Negative bias temperature instability; Niobium compounds; Process design; Random access memory; Titanium compounds; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on

Print_ISBN

0-7803-8528-4

Type

conf

DOI

10.1109/ICICDT.2004.1309933

Filename

1309933