• DocumentCode
    415632
  • Title

    Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies

  • Author

    Lin, Sheng-Chih ; Basu, Anirban ; Keshavarzi, Ali ; De, Vivek ; Mehrotra, Amit ; Banerjee, Kaustav

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
  • fYear
    2004
  • fDate
    25-29 April 2004
  • Firstpage
    74
  • Lastpage
    78
  • Abstract
    This paper introduces the idea of electrothermally coupled evaluation of junction temperature to accurately estimate the lifetime of interconnects under electromigration (EM) constraints in leakage dominant technologies. The junction temperature thus evaluated with our proposed methodology is incorporated into the interconnect temperature-rise equation (which includes Joule-heating) and is solved self-consistently with both unipolar and bipolar EM lifetime equations to estimate accurate interconnect metal temperature and to provide comprehensive design guidelines for maximum allowable current density in power/ground and signal lines.
  • Keywords
    CMOS integrated circuits; current density; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; leakage currents; nanotechnology; Joule-heating; comprehensive design guidelines; electromigration design rules; electrothermally coupled evaluation; interconnect temperature-rise equation; interconnects lifetime; maximum allowable current density; nanometer scale CMOS technologies; off-state leakage current; CMOS technology; Electromigration; Electrothermal effects; Equations; Guidelines; Land surface temperature; Leakage current; Life estimation; Lifetime estimation; Signal design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International
  • Print_ISBN
    0-7803-8315-X
  • Type

    conf

  • DOI
    10.1109/RELPHY.2004.1315304
  • Filename
    1315304