Title :
Effect of magnetic field on plasma damage during VIA etching in sub-micron CMOS technology
Author :
Kim, Nam Sung ; Yoon, Hyun Gu ; Lee, Chee Kiat ; Zhao, Jing ; Tuck, Chow Yew ; Cheah, Yong Sean ; Wong Wing Yew ; Southworth, Paul ; Sang Hyun Han ; Pey, K.S.
Author_Institution :
Process Integration Dept., Syst. on Silicon Manuf. Co. Pte. Ltd., Singapore, Singapore
Abstract :
The impact of VIA etching process with magnetic field and main etch time on plasma damage to gate oxide of n/pMOS capacitors has been intensively investigated. It is reported that the lower magnetic field during VIA etching process can reduce the plasma charging damage to the gate oxide. The magnetic field and main etch time at VIA etching are dominant factors to reduce the plasma charging damage.
Keywords :
CMOS integrated circuits; MOS capacitors; contact resistance; integrated circuit reliability; ion beam effects; radiation hardening (electronics); sputter etching; VIA etching; gate oxide; magnetic field; n/pMOS capacitors; plasma charging damage; plasma damage; sub-micron CMOS technology; CMOS technology; Capacitors; Diodes; Etching; MOS devices; Magnetic fields; Plasma applications; Plasma devices; Plasma measurements; Protection;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International
Print_ISBN :
0-7803-8315-X
DOI :
10.1109/RELPHY.2004.1315441
