Thermal degradation of DRAM retention time: Characterization and improving techniques

Author

Kim, Y.I. ; Yang, K.H. ; Lee, W.S.

Author_Institution

DRAM Dev. Div., Samsung Electron. Co. Ltd., Gyeonggi-Do, South Korea

fYear

2004

fDate

25-29 April 2004

Firstpage

667

Lastpage

668

Abstract

Variation of DRAM retention time and reliability problem induced by thermal stress was investigated. Most of the DRAM cells revealed 2-state retention time with thermal stress. The effects of hydrogen annealing condition and fluorine implantation on the variation of retention time and reliability are discussed.

Keywords

DRAM chips; annealing; fluorine; integrated circuit reliability; ion implantation; passivation; thermal stresses; DRAM retention time; fluorine implantation; hydrogen annealing condition; reliability problem; thermal degradation; thermal stress; Annealing; Capacitors; Continuous wavelet transforms; Hydrogen; Manufacturing; Passivation; Random access memory; Silicon; Thermal degradation; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International

Print_ISBN

0-7803-8315-X

Type

conf

DOI

10.1109/RELPHY.2004.1315442

Filename

1315442

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=415658