• DocumentCode
    41591
  • Title

    Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit

  • Author

    Chih-Hao Chao ; Kun-Chih Chen ; An-Yeu Wu

  • Author_Institution
    Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    21
  • Issue
    11
  • fYear
    2013
  • fDate
    Nov. 2013
  • Firstpage
    2118
  • Lastpage
    2131
  • Abstract
    The 3-D network-on-chip (NoC) router is a major source of thermal hotspots, limiting the performance gain of 3-D integration. Due to the varying cooling efficiency of different silicon layers in 3-D NoC, the optimal criteria of traditional load balancing design (LBD) scheme and temperature balancing design (TBD) scheme may not be satisfied. To analyze the tradeoff between performance and temperature, we provide a new analytical model. The model shows that the LBD scheme and the TBD scheme can be considered as two corner cases in the design space, and design cases can be categorized by comparing the bandwidth bound and the thermal-limited bound. To find the optimal design criteria between the LBD and the TBD schemes in 3-D NoC, we propose a new routing-based traffic migration, vertical-downward lateral-adaptive proactive routing (VDLAPR), and buffer allocation methods, vertical buffer allocation (VBA). The VDLAPR algorithm enables to tradeoff between the LBD and the TBD schemes. The proposed VBA method mitigates the traffic congestion caused by traffic migration. To reach the optimal configuration, we propose a systematic design flow, which assists in finding the best design parameters in the expanded space between LBD and TBD. Based on the traffic-thermal co-simulation experiments, the achievable throughput can be improved from 2.7% to 45.2% using the proposed design scheme.
  • Keywords
    network routing; network-on-chip; resource allocation; 3D network-on-chip systems; LBD scheme; NoC; TBD scheme; VBA method; VDLAPR algorithm; bandwidth bound; buffer allocation schemes; design space; load balancing design scheme; performance gain; routing-based traffic migration; silicon layers; systematic design flow; temperature balancing design scheme; thermal hotspots; thermal limit; thermal-limited bound; vertical buffer allocation; vertical-downward lateral-adaptive proactive routing; Bandwidth; Cooling; Loading; Program processors; Resource management; Thermal loading; Throughput; 3-D IC; 3-D NoC; Buffer allocation; downward routing; network-on-chip (NoC);
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2227852
  • Filename
    6428725