Title :
MAP (mobile AGP processor) - a high performance integrated graphics module
Author :
Pendse, Raj ; Marcus, Bill ; Yee, M.H. ; Yun, J.S. ; Zahn, Bret ; Jafari, Bob ; Dewey, Tom ; Lau, Tim ; Michael, M. ; Singh, Inderjit ; Starr, O.
Author_Institution :
ChipPAC Inc., Fremont, CA, USA
Abstract :
A flip-chip multi-chip module has been developed for NVidia´s mobile AGP processor (MAP) family of integrated graphics subsystem products. The graphics subsystem consists of a high-end graphics processing unit (GPU) chip, four high-speed DDR memory components, forty passive components (consisting of resistors, capacitors and jumpers) and a heat spreader, integrated on two sides of a single high-density substrate, within the form factor of a JEDEC-standard 31 × 31 mm ball grid array (BGA) package. The package includes several innovative and unique technological features such as: (a) A graphics processor chip with approximately 1000 solders bumps that is flip chip attached on the ball-side of the BGA package. This is facilitated by bumped wafer thinning technology to achieve a bumped die thickness of 240 μm and a unique underfilling process for a thin die. (b) High speed DDR memory components in CSP packages that are mounted to the same substrate as the flip chip die but on the opposing side; the components are underfilled for high reliability. (c) A 2-2-2 build-up substrate that provides a high-speed interface between the memory components and the graphics chip located on opposing sides of the substrate; this also allows maximum utilization of the build-up layer density on both sides of the core. (d) A dual flow path cooling solution consisting of a heat spreader on the topside and direct thermal contact between the GPU and motherboard on the bottom side. (e) A unique assembly process that integrates flip chip technology, in-process electrical testing, and SMT processing in a streamlined flow to enable mass production of the package with yields above 99.5 % in high volume. In this paper, we present the development of this package covering design, assembly process development, and package structure optimization performed to enable high component-level reliability and a successful launch into production. We will present data covering the understanding of failure modes that led to the improvement of reliability and manufacturing robustness. Future evolution of the module architecture in graphics products will also be discussed.
Keywords :
ball grid arrays; chip scale packaging; computer graphic equipment; digital signal processing chips; failure analysis; flip-chip devices; integrated circuit design; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; microassembling; multichip modules; substrates; surface mount technology; 2-2-2 build-up substrate; 240 micron; BGA; GPU; MAP; NVidia mobile AGP processor; SMT processing; assembly process; assembly process development; bumped wafer thinning technology; chip scale packages; dual flow path cooling solution; failure modes; flip chip technology; flip-chip multi chip module; graphics processing unit; heat spreader; high component-level reliability; high performance integrated graphics module; high speed DDR memory components; improved manufacturing robustness; improved reliability; in-process electrical testing; integrated circuit design; integrated graphics subsystem products; package structure optimization; singular high-density substrate; standard JEDEC ball grid array package; thin die underfilling; Assembly; Capacitors; Chip scale packaging; Contacts; Cooling; Electronics packaging; Flip chip; Graphics; Resistance heating; Resistors;
Conference_Titel :
Electronic Components and Technology Conference, 2004. Proceedings. 54th
Print_ISBN :
0-7803-8365-6
DOI :
10.1109/ECTC.2004.1319308