A low-cost plated column bump technology for sub 100 μm and WLP applications

Column or pillar bumps were developed at least a decade ago and applied to innovative flip chip packaging of gallium arsenide power amplifiers. Availability of easy to use thick photoresists has revived interest in this alternative to the solder bump flip chip solder interconnects now widespread for performance or size driven silicon. Key drivers for new flip chip technologies in the context of silicon are underfill and low alpha issues arising from the shrink in die to substrate gap in proportion with a shrink in pitch of solder bumps down to 80 micron. For wafer level packaging a low cost approach to reduction of die to PCB mismatch strain is also desirable. Conventional plating processes have been modified to develop a low cost column bump structure plated on a wafer batch w/o resort to single wafer fountain plating. These modifications are found effective to plate up to 50 um high columns in an opening of 50 um dia. The columns can be capped with various solder pastes by printing. Non uniformity of plated column height is effectively ameliorated by the solder cap after reflow. Preliminary assembly and reliability have been completed and high temperature storage etc, are in progress. A key factor to improve reliability was found to be the shape of the solder joint after the chip join operation. This was achieved by developing an in-situ reflow process. Substantial reduction in bumping, assembly and substrate PCB costs are expected from this next - generation flip chip technology.