DocumentCode
415951
Title
In-process measurement of the interfacial fracture toughness for a sub-micron titanium thin film and silicon interface using a single-strip decohesion test
Author
Zheng, Jiantao ; Sitaraman, Suresh K.
Author_Institution
Comput.-Aided Simulation of Packaging Reliability Lab., Georgia Inst. of Technol., Atlanta, GA, USA
Volume
1
fYear
2004
fDate
1-4 June 2004
Firstpage
134
Abstract
The measurement of mode-mixity dependent interfacial fracture toughness (Γ) is necessary to predict the interface integrity and the component reliability of thin-film structures. A new approach, called the single-strip decohesion test (SSDT), eliminates shortcomings of the current testing methods. In this approach, a trilayer thin film structure is built to measure the interfacial fracture toughness. A highly stressed super layer, such as Cr, is used to drive the delamination and produces any mode mix at the crack tip. An isosceles triangle-shaped non-adhesive layer (10 to 50 nm thick) is sandwiched between the film of interest and the substrate to realize the contact area change along the crack direction. SSDT uses the change in crack surface area to vary the available energy per unit area for crack growth and thus to measure the interfacial fracture toughness. Common IC fabrication techniques are used to prepare the sample and execute the test, thereby making the test compatible with current microelectronic or MEMS facilities. The design, preparation, and execution of the SSDT are discussed. Finite element models of the SSDT sites are used to extract fracture parameters, and interfacial fracture toughness results are provided for a Ti/Si interface at several mode mixes.
Keywords
chromium; crack-edge stress field analysis; delamination; elemental semiconductors; finite element analysis; fracture toughness testing; interface structure; silicon; thin films; titanium; 10 to 50 nm; Cr-Ti-Si; IC fabrication techniques; MEMS; SSDT; component reliability; crack growth; crack surface area change; crack tip mode mix; finite element model; highly stressed super layer; in-process measurement; interface integrity; interfacial delamination; interfacial fracture toughness measurement; microelectronics; mode-mixity dependent interfacial fracture toughness; single-strip decohesion test; titanium thin film/silicon interface; trilayer thin-film structures; Area measurement; Chromium; Delamination; Integrated circuit testing; Semiconductor thin films; Silicon; Substrates; Surface cracks; Titanium; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2004. Proceedings. 54th
Print_ISBN
0-7803-8365-6
Type
conf
DOI
10.1109/ECTC.2004.1319326
Filename
1319326
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