Chip integration of Sea of Leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics

This paper describes the process and assembly integration of Sea of Leads (SoL) with an Intel chip. A primary goal of the research was to study the issues involved in reconciling the fabrication and assembly requirements of compliant leads, such as SoL, with those of standard semiconductor processes and standard chip assembly techniques. The study was motivated in-part by the potential failure of the low-k interlayer dielectric in microprocessors as a result of high mechanical stresses due to the coefficient of thermal expansion (CTE) mismatch between the chip and the board. SoL, and other compliant interconnections, mitigate this problem by mechanically decoupling the chip and the board. We show that while the compliant leads offer advantages over C4 technology, there is much to consider during the series of steps needed to transform the fully intact dice at the wafer level to dice that are assembled onto the board. The use of an encapsulation film over the leads during wafer sawing is shown to be necessary for slippery leads and other freestanding compliant leads. Compliant leads on the edges of the chip tend to extend beyond the active region of the dice. The use of the correct flux when the leads are encapsulated with nickel-oxide nonwettable layer is shown to be essential for a successful wafer-level solder reflow. Thermo-compression bonding is shown to be a promising assembly technique for SoL because it can overcome the problem of non-uniform height of the solder bumps on the board.