Silicon modeling of nanometer systems-on-chip

Given that more than half of mixed signal designs are failing first silicon, SoC designs require a comprehensive approach to parasitic extraction that satisfies the needs for accuracy, performance and detailed analysis. Parasitic extraction tools need to provide not only comprehensive evidence of unintentional parasitic effects, but also accurate data for accurate analysis. These analysis requirements may include: static timing (C or RC) for traditional timing analysis and overall net delay; dynamic timing (C or CRC) for propagation delay with all circuitry active; Noise (RC) for crosstalk and signal integrity issues; Power (R) for IR drop and hotspots; and reliability (R) for yield analysis and electromigration. The design styles found in SoCs, be they analog, memory or full custom, etc., require a comprehensive approach to extraction. Designers need an LVS parasitic extraction tool suite that provides gate-level, transistor level, and mixed-level analysis, plus accuracy, capacity and performance across all design styles to obtain accurate silicon modeling.