An efficient VLSI implementation of MC interpolation for MPEG-4

Quarter sample mode interpolation is one of critical paths of the MPEG-4 decoder because it has a finite impulse response (FIR) digital filter which is a computationally expensive process. Normal FIR architectures are not suitable for this application due to the set of short input data streams. After reforming a referenced pure systolic FIR, the paper gets an efficient architecture of quarter sample mode interpolation and the architecture is suitable for VLSI. Experimental result shows that the proposed architecture can satisfy MPEG-4 decoder applications.