DocumentCode
416189
Title
FPGA implementation of space-time block coding systems
Author
A, M. Baghaie ; Kuo, S. ; McLoughlin, I.V.
Author_Institution
Dept. of Electr. & Comput. Eng., Canterbury Univ., Christchurch, New Zealand
Volume
2
fYear
2004
fDate
31 May-2 June 2004
Firstpage
591
Abstract
In this paper, the implementation of space-time block coding systems is discussed, particularly through the use of programmable logic such as FPGAs. The rationale for choice of such devices in preference to DSPs is discussed followed by an analysis of the design and development process and the methodologies employed in the design process. An example space-time system, time-reversal space-time block coding (TR-STBC) is discussed and implementation described.
Keywords
block codes; field programmable gate arrays; radiocommunication; space-time codes; DSP; FPGA implementation; programmable logic; space-time block coding system; space-time processing; time-reversal space-time block coding; wireless channel; Block codes; Clocks; Digital signal processing; Field programmable gate arrays; Hardware; Logic devices; Process design; Programmable logic arrays; Programmable logic devices; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Emerging Technologies: Frontiers of Mobile and Wireless Communication, 2004. Proceedings of the IEEE 6th Circuits and Systems Symposium on
Print_ISBN
0-7803-7938-1
Type
conf
DOI
10.1109/CASSET.2004.1321957
Filename
1321957
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