Title :
A method for correcting the functionality of a wire-pipelined circuit
Author :
Nookala, Vidyasagar ; Sapatnekar, Sachin S.
Author_Institution :
University of Minnesota, Minneapolis, MN
Keywords :
Circuit testing; Clocks; Delay; Flip-flops; Frequency; Integrated circuit interconnections; Permission; Pipeline processing; Throughput; Wire;
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-51183-828-8
