DocumentCode

416312

Title

Architecture-level synthesis for automatic interconnect pipelining

Author

Cong, Jason ; Fan, Yiping ; Zhang, Zhiru

Author_Institution

University of California, Los Angeles, CA

fYear

2004

fDate

7-11 July 2004

Firstpage

602

Lastpage

607

Keywords

Algorithm design and analysis; Clocks; Delay effects; Flip-flops; Frequency; Integrated circuit interconnections; Permission; Pipeline processing; Wires; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2004. Proceedings. 41st

Conference_Location

San Diego, CA, USA

ISSN

0738-100X

Print_ISBN

1-51183-828-8

Type

conf

Filename

1322553