Statistical gate delay model considering multiple input switching

There is an increased dominance of intra-die process variations, creating a need for an accurate and fast staristical riming analysis. Most of the recent proposed approaches assume a Single Input Switching model. Our experiments show that SIS underestimates the mean delay of a stage by upto 20% and overestimates the standard deviation upto 26%. We also show fhar Multiple Input Switching has a greater impacr on sratisrical timing, rhan regular static timing analysis. Hence, we propose a modeling technique for gate delay variability, considering MIS. Our model can he efficiently incorporated into most of the statistical riming annlysis frameworks. On average over all rest cases, our approach underesrimares mean delay of a sfage by 0.01 % and overestimates the standard deviation by only 2%. hence increosing the robustness to process variations. Our modeling technique is independent of the deterministic MIS model, and we show that its sensitivity to variations in the MIS model is small.