DocumentCode :
416341
Title :
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Author :
Srivastava, Ashish ; Sylvester, Dennis ; Blaauw, David
Author_Institution :
University of Michigan, Ann Arbor, MI
fYear :
2004
fDate :
7-11 July 2004
Firstpage :
783
Lastpage :
787
Keywords :
Algorithm design and analysis; Benchmark testing; Circuit testing; Design optimization; Energy management; Flip-flops; Minimization; Permission; Power dissipation; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
ISSN :
0738-100X
Print_ISBN :
1-51183-828-8
Type :
conf
Filename :
1322588
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=416341
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