Title :
Impact of
Interference on Charge-Trapping NAND Flash Memory Devices
Author :
Yi-Hsuan Hsiao ; Hang-Ting Lue ; Wei-Chen Chen ; Kuo-Pin Chang ; Bing-Yue Tsui ; Kuang-Yeu Hsieh ; Chih-Yuan Lu
Author_Institution :
Macronix Int. Co., Ltd., Hsinchu, Taiwan
Abstract :
The impact of adjacent word-line´s pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.
Keywords :
flash memories; logic gates; three-dimensional integrated circuits; 3D CT NAND flash; Vpass interference impact; charge-trapping NAND flash memory devices; double-gate architecture; field penetration impact; gate control ability; pass gate voltage interference; pitch scaling; threshold voltage; Computer architecture; Flash memories; Interference; Junctions; Logic gates; Materials; Microprocessors; Charge-trapping; Fringing field; SONOS; fringing field; interference; pass gate voltage;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2015.2398193