DocumentCode
416961
Title
A hardware depressing synapse and its application to contrast-invariant pattern recognition
Author
Kanazawa, Y. ; Asai, T. ; Amemiya, Y.
Author_Institution
Hokkaido Univ., Sapporo, Japan
Volume
2
fYear
2003
fDate
4-6 Aug. 2003
Firstpage
1558
Abstract
Analog circuits for depressing synapses are proposed for emulating the dynamic properties of neural networks using dynamic neurons. Although the circuits have few MOS transistors, they mimic well the dynamic properties of depressing synapses. A simple neural network using depressing synapses is introduced for evaluating the performance of hardware depressing synapses. We show that a device using the neural network can perform contrast-invariant pattern recognition based on a neuromorphic processing architecture.
Keywords
MOSFET; analogue circuits; neural nets; pattern recognition; MOS transistors; analog circuits; contrast invariant pattern recognition; dynamic neurons; dynamic properties; hardware depressing synapse; neural networks; neuromorphic processing architecture; performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
SICE 2003 Annual Conference
Conference_Location
Fukui, Japan
Print_ISBN
0-7803-8352-4
Type
conf
Filename
1324204
Link To Document