A 28mW 10b 80MS/s pipelined ADC in 0.13μm CMOS

This paper describes the implementation of a fully integrated pipelined ADC implemented in a standard 0.13μm CMOS technology. In contrast to a standard 1.5bit pipeline architecture several design changes are proposed. The resolution of 10 bit and the low power of 28 mW have been achieved by using a multi bit architecture without a dedicated front-end sample and hold. The multi bit architecture leads to the low opamp count of three for the complete ADC compared to eight of a standard 1.5 bit architecture. The power consumption of this work is less than half compared to previous as stated in A. Abo and P. Gray (1999), L. Singer et al. (2000), B. M. Min et al. (2003) and S. M. Yoo et al. (2003). The proposed architecture works up to input signal frequencies of 150 MHz. Additionally there is an interstage scaling applied to all stages. This scaling is very effectively implemented by using the same unary cell for all stages. The cell is used multiple at higher stages.