A background digital self-calibration scheme for pipelined ADCs based on transfer curve estimation

The pipelined architecture is one of the most popular ADC architecture. Various linear and nonlinear errors limit the pipelined ADC´s performance. Many calibration algorithms to calibrate this architecture ADC have been reported in literature. In this paper, a new background self-calibration scheme for pipelined ADCs is presented and this calibration scheme can correct both linear and nonlinear errors in the pipelined data path. Simulation shows that with this calibration scheme, the ENOB of a 16-bit pipelined ADC can be improved from 10 bits to about 15 bits.