High-PSR bias circuitry for NTSC sync separation

This paper presents a simple and bias generation circuitry (BGC) with temperature compensation. The proposed BGC utilizes step-down regulators and a bandgap-based bias with cascade current control. The clamping voltages required for sync separation from an NTSC signal are generated. Detailed PSR (power rejection ratio) analysis of the proposed BGC is also derived to circumscribe the clamping voltage variation. The worst variation of the proposed design verified by HSPICE post-layout simulations is 4.2% given a [-50°C, +150°C] temperature range, and a VDD(=5V) +10%.