DocumentCode
417988
Title
On mismatch properties of MOS and resistors calibrated ladder structures
Author
Linares-Barranco, Bernabé ; Serrano-Gotarredona, Teresa ; Serrano-Gotarredona, Rafael ; Vicente-Sànchez, Gustavo
Author_Institution
Instituto de Microelectron. de Sevilla, Spain
Volume
1
fYear
2004
fDate
23-26 May 2004
Abstract
The mismatch behaviour of MOS and resistor based calibrated ladder structures, used in arrays of DACs, is studied theoretically and experimentally. It is found that the calibrated DAC worst case output current standard deviation is approximately 1/3 that of its individual components. MOS experimental measurements illustrate the discussed mismatch behaviour. Directions on how to design ladder DACs for a target precision are provided.
Keywords
calibration; digital-analogue conversion; impedance matching; resistors; MOS; calibrated DAC; calibrated ladder structures; ladder DAC; mismatch behaviour; resistors; CMOS process; Calibration; Circuit synthesis; Current measurement; Digital control; Digital-analog conversion; Gaussian distribution; MOSFETs; Resistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328210
Filename
1328210
Link To Document