High-voltage-tolerant power supply in a low-voltage CMOS technology

A power supply circuit that is tolerant of supply voltages up to twice the process limit for individual CMOS transistors is presented. The circuit demonstrates an economical and reliable way to accommodate high-voltage power sources in highly integrated power management ICs. A combination of a cascode topology and a bias voltage tracking technique ensures that each individual transistor remains within its operating limits. The described approach and circuits were implemented in a power management IC for cellular phones using a 5 V CMOS process. The implemented power supply is tolerant of input voltages up to 12 V and passes operational life and reliability tests. Simulation and measurement data for steady-state and power-up transient conditions confirms that the opening conditions of the internal components are safe for all possible combinations of external supplies and loads.