A low-power 10-bit continuous-time CMOS ΣΔ A/D converter

This paper presents the design of a third-order low-pass ΣΔ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using G_m - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well as transistor level design issues for power efficiency is discussed. A prototype ΣΔ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 μm CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 dB at a sampling rate of f_s = 1.4 MHz, while drawing a bias current of 60 μA from a modest supply voltage of 1.8 V, thus consuming 108 μW of power.