Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters

A quasi-parallel matching architecture for CDMA matched filters has been proposed aiming at high-speed and flexible multi-path detection. In the architecture, a drastic reduction in the hardware volume has been achieved as compared with a fully-parallel matching architecture according to Okada and Shibata (1999), while preserving the equivalent performance. The feasibility of the chip implementation has been examined based on the experimental results obtained from the floating-gate-MOS matched filters fabricated in a 0.35-μm CMOS technology. As a result, the system is estimated to dissipate 31.0 mW occupying 4 mm₂ chip area for the 512-chip length correlation at a rate of 4.096 Mchips/s and four samples/chip.