Low thermal error sampling comparator for accurate settling measurements

A new sampling comparator design employing a signal-dependent biasing scheme is described. The dynamic bias significantly reduces signal-induced thermal error in the comparator. The circuit design approach is applicable to comparators intended for use in equivalent-time, successive approximation analog-to-digital conversion where required bandwidths may exceed 1 GHz and digitizing resolution may be as high as 16 bits. The technique is well suited for high accuracy settling measurements where thermal tail error can undermine the achievable settling response of an otherwise high bandwidth sampler. The new comparator design is a logical follow-up to previous work in which front-end bias on/off switching was employed. A prototype circuit has been fabricated in a 1.5 μm BiCMOS process. In the prototype device, the technique reduces settling error of 300 ns from 800 μV/V from dc to 1 MHz.