An improved algorithmic ADC clocking scheme

An improved algorithmic ADC clocking scheme is presented. Using an optimized clock generator, a significant improvement in conversion speed is achieved in the converter. This proposed optimized clock generator removes the wasted time which exists during all conversion cycles except for the first one. This technique can improve the conversion speed up to 82% compared to conventional algorithmic ADCs. Alternatively, static power consumption can also be reduced for a given conversion speed. An algorithmic ADC using the new clocking scheme is validated using MATLAB behavioral simulations.