DocumentCode
418027
Title
Compact CMOS linear transconductor and four-quadrant analogue multiplier
Author
Panovic, Mladen ; Demosthenous, Andreas
Author_Institution
Dept. of Electron. & Electr. Eng., Univ. Coll. London, UK
Volume
1
fYear
2004
fDate
23-26 May 2004
Abstract
This paper describes a low voltage/low power MOS linear transconductor which can be configured to realize a square-law function circuit and a four quadrant analogue multiplier. The compact analogue computation cells described are particularly suited to parallel processing systems. The circuits were fabricated using a 0.8 μm CMOS process and operate from a 2 V power supply.
Keywords
CMOS analogue integrated circuits; analogue multipliers; integrated circuit design; low-power electronics; 0.8 micron; 2 V; CMOS process; analogue computation cells; circuit fabrication; compact CMOS linear transconductor; four-quadrant analogue multiplier; low power MOS linear transconductor; low voltage MOS linear transconductor; parallel processing systems; power supply; square-law function circuit; Analog computers; CMOS process; Circuits; Concurrent computing; Low voltage; MOSFETs; Power supplies; Threshold voltage; Transconductance; Transconductors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328287
Filename
1328287
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