A low-voltage low sensitivity sinusoidal VCO for DPLL realizations

Author

De Lima, Jader A. ; Agostinho, Peterson R.

Author_Institution

Dept. of Electr. Eng., Univ. Estadual Paulista, Guaratingueta, Brazil

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f₀ is first-order independent of V_DD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm². Nominal f₀ is 1 MHz, with K_VCO=8.4KHz/mV. Measured sensitivity to V_DD is below 2.17, while phase noise is -86dBc at 100 kHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and V_DD=3.3V, with a linear frequency-span of 13.2 MHz-61.5 MHz.

Keywords

CMOS digital integrated circuits; digital phase locked loops; operational amplifiers; voltage-controlled oscillators; 0.35 micron; 0.8 micron; 1 MHz; 100 kHz; 13.2 to 61.5 MHz; CMOS process; OTA input devices; RHP poles; digital phase locked loop; gate-drain capacitances; linearly tunable OTA-C VCO; mixed-mode designs; oscillation frequency; quasisinusoidal OTA-C VCO; triode-region transconductors; voltage controlled oscillator; Analytical models; CMOS process; Capacitance; Frequency; Noise measurement; Phase measurement; Phase noise; Prototypes; Transconductors; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328313

Filename

1328313