Title :
On-chip calibration technique for delay line based BIST jitter measurement
Author :
Nelson, Bryan ; Soma, Mani
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
On-chip calibration technique for delay line based time-to-digital converters (TDC) used in jitter measurement built-in self-test (BIST). The proposed technique utilizes pulse width modulation (PWM) to generate accurate voltages to control delay elements within the TDC. Calibration is performed in three stages; accuracy fine-tuning, measurement dynamic range adjustment, and characteristic curve generation. Preliminary simulation results using the calibration technique on a modified Vernier delay line (VDL) BIST provided a cycle-to-cycle jitter resolution of ∼5 ps. The calibration design consists of digital CMOS components and has a potential die area of 0.03μm2. Calibration time is less than 1.1ms and only a single external calibration input pin is required in addition to the existing BIST.
Keywords :
analogue-digital conversion; built-in self test; calibration; delay lines; jitter; pulse width modulation; BIST jitter measurement; CMOS components; Vernier delay line; accuracy fine-tuning; built-in self-test; calibration design; curve generation; cycle-to-cycle jitter resolution; delay elements; measurement dynamic range adjustment; on-chip calibration technique; pulse width modulation; time-to-digital converters; Built-in self-test; Calibration; Delay lines; Dynamic range; Jitter; Performance evaluation; Pulse generation; Pulse width modulation; Space vector pulse width modulation; Voltage control;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328352